Autonomous Harness Engineering Architecture
A hardware verification architecture showing machine-readable specs, AI-driven harness generation, UVM agents, UVM testbench, DUT simulation, logs, LLM verification, results, coverage database, and closed-loop feedback.
AUTONOMOUS
HARNESS
ENGINEERING ARCHITECTURE
Machine-
Readable
Specs
(IP-XACT/JSON)
AI-Driven
Harness
Generator
UVM Agents
(Drivers,
Monitors)
UVM Testbench
Stimulus
Generator
DUT
Device
Under Test
LOC
Simulation
Logs
Py
Python
Golden Model
Scoreboards
& Predictors
LLM
Verification
Agent
Automated Root Cause
Analysis (RCA)
Verification
Results
(Reports,
Coverage)
Coverage
Database
UCDB
SVA Generation 설명은 이 노드를 3번 클릭하면 열립니다.
SVA
Generation
Spec Schema
Generated
Harness Code
Stimulus
Data
Stimulus
Data
Log
Data
Coverage
Information
Result
Data
Result
Data
Feedback
Metrics
Closed-Loop Feedback